Types of element?

1. Active and Passive element:

Active devices are the one which generates (or) amplify (or) rectify any signals (Voltage source, Current source, Diode, Transistor, DIAC, SCR, Op-Amp, etc)

Rest all devices are called a passive device (R, L, C, Transformer).

Note: Amplification here is in terms of the power signal and hence transformer cannot be put under the category of the active device as the power is constant in both the primary and secondary side of the transformer (I1V1 = I2V2).

2. Linear and Non-Linear:

Linear devices are the one which obeys the law of superposition and homogeneity. 

(Or) To put this simply, any straight line passing through the origin is called a linear element (R, L, C).

Non-linear element examples are diode, SCR, DIAC, etc.

3. Bilateral and Unilateral:

Any bilateral element (e.g. R, DIAC) will have similar characteristics in the 1st and 3rd quadrant of the graph else it will be a unilateral element (e.g. Diode).

4. Time-Variant and Time-Invariant

5. Lumped and Distributed

Let's understand these concepts on a graph (I vs V):-

Latch-Up Effect?

As can be seen in the above snapshot, resistance connected to the bases of NPN transistors and collectors of the PNP transistors greatly influences both ESD and Latch-Up effect in the layout. Furthermore, latch-up is sensitive to layout and hence most often solved at the layout level when doing the physical implementation of the design.

What is latch-up?
Latch-up is the creation of low impedance path between the power supply rails (e.g. vdd to gnd in the above case). It is caused when the parasitic BJT structures within an IC are triggered when a current/voltage is applied as stimulus in the input, output or I/O pin.

Sometime it also happen that the latch-up occur only while the pulse stimulus is connected to the IC and returns back to normal level once the stimulus is removed. Such an effect is called temporary (or) transient latch-up.

While a true latch-up is a one which remains even after the stimulus is removed. In such scenarios to remove the low impedance path between the power rails, a power supply shutdown is required.

How does it occur?
Latch-up is a regenerative process that occur when a pnpn structure (aka silicon controlled rectifier (SCR)) is formed. It is composed of parasitic npn and pnp transistor. 

To avoid latch-up:

1. Vpnpn <= Vs (Sustaining Voltage)
2. Injecting current < Holding current (IH)

Prevention Technique:

1. Surround the transistor with guard rings.
2. Reduce Rn and Rp. This will cause more current requirement for latch-up to occur.

What are guard rings? 

Guard rings are used to collect majority (or) minority carriers flowing in the silicon. Tuning the doping level of the guard ring material helps in increasing or decreasing the resistance in the area of guard ring.

Shallow Trench Isolation (STI)

• Isolation technique to prevent current leakage between adjacent semiconductor device.
• Hence, prevents latch-up.
• MOSFET's are also called self-isolating devices but as the transistor size decreases the use of reverse bias pn-junction to isolate transistor becomes impractical.
• STI allows closer spacing of transistors.
• In scenarios as n+ & p+ spacing gets smaller, birds beak shape characteristic is formed which leads to undesirable stress effects in the transistor. 
• STI has the advantage of minimizing the heat cycle needed for n+ and p+ isolation.
• Additionally, it also reduces substrate noise coupling. 

Submicron, Deep Submicron, Ultra Deep Submicron

CMOS Technology Categories:-

1. Submicron: L >= 350 nm
2. Deep Submicron: 100 nm <= L <= 350 nm
3. Ultra Deep Submicron: L <= 100 nm

Source: https://aicdesign.org/