Learn Verilog

History:-

• Invented in 1984 by Phil Moorby.
• From 1984 - 1989, Verilog was owned by Gateway Design Automation.
• In 1989, Cadence Design Systems acquired Gateway Design Automation.
• Later Verilog was opened to the public domain.
• In 1995, Verilog was made an IEEE standard commonly referred to as Verilog-95.
• In 2005, SystemVerilog was also developed as a superset of Verilog by Accellera.
• In 2009, Verilog and SystemVerilog were merged to form one IEEE standard.

What is Verilog?

Verilog is a programming language that was invented to enable modeling and behavioral simulation of logic designs. It allows different levels of abstraction based on the design requirement (e.g. Gate level netlist, RTL level, etc).

Note:- Unlike VHDL, Verilog is case-sensitive.

Verilog is used for hardware modeling, testbench modeling, board-level designs, system-level designs, and transistor switch-based designs. Verilog supports hierarchical design entry which enables easier designing, verification, and debugging. 

Advantage:-

• Easier than VHDL.
• Flexible.
• Provide multiple methods to code the same functionality.
• Used for logic synthesis, timing analysis, gate-level simulation, and developing test methods.

Introduction to Verilog

• Name all Verilog Standards?
• What are Structural and Behavioral Verilog?
  
• Levels of Abstraction in Verilog?
  
• Keywords vs Identifier (Verilog)?
  
• Comments (Verilog)?
  
• Verilog data representation?
  
• Inference vs Instantiation (Verilog)?
  
• What are Data Objects (Verilog)?
  
• Reg vs Wire (Verilog)?
  
• Buses in Verilog?
  
• Arrays, Memory and Strings in Verilog?