Buses in Verilog?

A  bus is a collection of bits. 

Declaration: <type><width or range><identifier>

Bus of wire data type:-

wire [7:0] val;

wire signed [7:0] val;

Bus of reg data type:-

reg [7:0] val;

reg signed [7:0] val;

Bit Select:- Any single bit within a vector (or) an array can be referenced individually.

wire [7:0] val_1;

wire [15:0] val_2;

assign val_1[6] = val_2[12];

Part Select:- Any group of nets in a bus can be referenced as a part select.

• The direction of part select must match the original bus declaration.
• The bounds of the part select must be within the original bus.

reg [7:0] val = 8'b10101010

Value of part select val[3:0] ==> has value of 10 (1010)