Verilog data representation?

Each bit is treated as data in the Verilog language. Each bit can support any of the following 4 logic values which are: 0, 1, ‘X’ (unknown or uninitialized), ‘Z’ (high impedance).

Syntax for declaring a number: <size><base format><number>

Explicitly-Sized Numbers: Here we have explicitly specified the size for the number;

6’b101101 -> 6-bit binary value

8’sh4a -> 8-bit signed hex value

16’Hfa2z -> 16-bit hex value

** 8’b1010 -> 0000_1010 (automatically zero-extended)

** 4’b10110111 -> 0111 (automatically extra bit's truncated)

Implicitly-Sized Numbers:

 ** When size parameter is not specified, default value of 32-bit is considered for internal compiler.

‘o12 -> 32-bit octal value

‘shab11 -> 32-bit signed hex value

3674 -> 32-bit signed decimal