What are Data Objects (Verilog)?

Data Objects:- These enable the change in state and passing of data from one point to another in logic design.

Two main types of data objects are:

1. Variables

• Evaluates when a procedural block executes (always or initial)
• It is procedural – stores and holds the value until its next assignment.

e.g.: reg, integer, real, time, realtime

• Integer: Represent integer value (e.g. integer a = 7;)
• Real: Used to model floating-point values (not synthesizable) (e.g. real val_1 = 3.65;)
• Time: Used to represent delay and sequencing (not synthesizable) (e.g. time delay_1 = 2ns;)
• Realtime: Store real value of simulation time.

2. Nets

• Evaluates when the input changes.
• It is structural – i.e. it connects a driver (or multiple drivers) to the receiver.
• There are eight data types of nets used for hardware modeling.

e.g.: wire, tri, wand, triand, wor, trior, tri0, tri1, trireg, supply0, supply1

 ** In general, only wire (i.e. point-to-point connections) is used for FPGA-based synthesis enabling source-code portability.