Reg vs Wire (Verilog)?

Reg Data Type:-

• The most commonly used variable data type.
• Can hold 0,1, X, Z values. ** Use range declaration for more bits
• Doesn't signify what type of value it will hold.
• Not to be confused with a register.
• Used to model storage elements.

e.g.: D-flip flop output is declared as reg and it will hold the value until the next positive clock edge arrives.

module dff( input d_in, clk, output reg q_out);

always @ (posedge clk)

q_out = d_in;

endmodule

Wire Data Type:-

• Most popular net data type.
• Default data type.
• Assigned using the 'assign' statement.
• Continuously updated based on the driver value.

e.g.: 

module mux2x1( input a, b, sell, output wire y);

assign y = (a & sel) | (b & ~sel);

endmodule

Reg data type is used whenever a data object is assigned within a Verilog procedural block (like always and initial).