What is FSM and what are its types?

FSM: Finite State Machine

It is a sequential circuit consisting of a combinational circuit, a storage element, and a feedback path from output to the input. Change in FSM state from one state to another is called transition.

FSM are of two types:

1. Mealy Machine: Output is a function of the current state and the applied input.

2. Moore Machine: Output is a function of the current state only.

State Diagram: It describes the behavior of a finite state machine. 

Verilog Module?

The basic unit of logic description which contains all the information required for modeling the hardware.

It starts with the 'module' keyword and end with the 'endmodule' keyword.

Syntax: 

module <module_name> (port declaration);

----------

----------

endmodule

Arrays, Memory and Strings in Verilog?

Arrays: Collection of objects of the same data type.

e.g.:

reg [7:0] arr; ==> 8-bit vector (or) bus of reg data type 

reg arr [7:0]; ==> array of 8 one-bit element

Memory: A memory structure can be created using arrays.

-> Memory structure using a 2-dimensional array: reg [0:7] memo [0:3];

-> Memory structure using a multi-dimensional array: reg [0:7] memo [0:3] [0:3] [0:3];

Strings: Group of characters enclosed in double quotation.

myString = "Welcome to VLSI Digest";

Buses in Verilog?

A  bus is a collection of bits. 

Declaration: <type><width or range><identifier>

Bus of wire data type:-

wire [7:0] val;

wire signed [7:0] val;

Bus of reg data type:-

reg [7:0] val;

reg signed [7:0] val;

Bit Select:- Any single bit within a vector (or) an array can be referenced individually.

wire [7:0] val_1;

wire [15:0] val_2;

assign val_1[6] = val_2[12];

Part Select:- Any group of nets in a bus can be referenced as a part select.

• The direction of part select must match the original bus declaration.
• The bounds of the part select must be within the original bus.

reg [7:0] val = 8'b10101010

Value of part select val[3:0] ==> has value of 10 (1010)

Reg vs Wire (Verilog)?

Reg Data Type:-

• The most commonly used variable data type.
• Can hold 0,1, X, Z values. ** Use range declaration for more bits
• Doesn't signify what type of value it will hold.
• Not to be confused with a register.
• Used to model storage elements.

e.g.: D-flip flop output is declared as reg and it will hold the value until the next positive clock edge arrives.

module dff( input d_in, clk, output reg q_out);

always @ (posedge clk)

q_out = d_in;

endmodule

Wire Data Type:-

• Most popular net data type.
• Default data type.
• Assigned using the 'assign' statement.
• Continuously updated based on the driver value.

e.g.: 

module mux2x1( input a, b, sell, output wire y);

assign y = (a & sel) | (b & ~sel);

endmodule

Reg data type is used whenever a data object is assigned within a Verilog procedural block (like always and initial).

What are Data Objects (Verilog)?

Data Objects:- These enable the change in state and passing of data from one point to another in logic design.

Two main types of data objects are:

1. Variables

• Evaluates when a procedural block executes (always or initial)
• It is procedural – stores and holds the value until its next assignment.

e.g.: reg, integer, real, time, realtime

• Integer: Represent integer value (e.g. integer a = 7;)
• Real: Used to model floating-point values (not synthesizable) (e.g. real val_1 = 3.65;)
• Time: Used to represent delay and sequencing (not synthesizable) (e.g. time delay_1 = 2ns;)
• Realtime: Store real value of simulation time.

2. Nets

• Evaluates when the input changes.
• It is structural – i.e. it connects a driver (or multiple drivers) to the receiver.
• There are eight data types of nets used for hardware modeling.

e.g.: wire, tri, wand, triand, wor, trior, tri0, tri1, trireg, supply0, supply1

 ** In general, only wire (i.e. point-to-point connections) is used for FPGA-based synthesis enabling source-code portability.

Inference vs Instantiation (Verilog)?